The present invention relates to a method for adaptively placing cells and changing the circuit during the synthesis process of an integrated circuit design.
A highly specialized field, commonly referred to as xe2x80x9celectronic design automationxe2x80x9d (EDA), has evolved to handle the demanding and complicated task of designing semiconductor chips. In EDA, computers are extensively used to automate the design process. Computers are ideally suited to performing tasks associated with the design process because computers can be programmed to reduce or decompose large, complicated circuits into a multitude of much simpler functions. Thereupon, the computers can be programmed to iteratively solve these much simpler functions. Indeed, it has now come to the point where the design process has become so overwhelming that the next generation of integrated circuit (IC) chips cannot be designed without the help of computer-aided design (CAD) systems.
Typically, the design process begins with an engineer conceiving and defining the performance specification of the new IC chip. A high level language is used to translate this specification into functional criteria which are fed into a logic synthesis program. Based thereon, the synthesis program generates a netlist containing a collection of gates or cells in terms of a particular semiconductor technology (e.g., very large scale integrationxe2x80x94VLSI). This netlist can be regarded as a template for the realization of the physical embodiment of the integrated circuit in terms of transistors, routing resources, etc. Next, a physical design tool is used to place and route the IC chip. It determines the physical pinouts, wiring, interconnections and specific layout of the semiconductor chip. Once the physical layout is complete, the IC chip can be fabricated.
As a software tool, synthesis is often used to predict performance characteristics by estimating the capacitances associated with wires in the design. The capacitance at a wire is based on historical data derived from statistical samplings of the average or typical capacitances experienced for similar wires in previous designs. Once the wires and their associated capacitances are known, mathematical models can be constructed to predict the circuit""s behavior. For example, a typical tool can be used to check the chip""s timing.
In the past, when semiconductor chips were simpler and less complex, the synthesis tool was able to predict the performance characteristics fairly accurately. However, advances in semiconductor technology have led the way towards more versatile, powerful, and faster integrated circuit (IC) chips. The trend is towards even larger, more complex and sophisticated IC chips in an effort to meet and improve upon the demands imposed by state-of-the-art performance. Today, a single IC chip can contain upwards of millions of transistors. As the complexity, functionality, and size of these chips increase, it is becoming a much more difficult task to estimate the capacitances associated with the multitudes of wires. The accuracies of the performance predictions have been seriously degraded.
Thus there is a need for some method which can be used to more accurately predict the performance of a synthesized design. The present invention provides a solution, whereby the synthesis and rough placement functions are combined into an integrated framework. With the present invention, the placement adapts to changes made to the netlist (e.g., creation, addition, modification, and deletion of nets and/or cells). Two mechanisms, cell separation and device sizing, are adaptively controlled to achieve convergence between the synthesis estimate and the extraction estimate after full place and route.
The present invention pertains to a process for the synthesis and rough placement of an IC design. Initially, a synthesis tool is used to generate a netlist according to HDL, user constraint, and technology data and physical constraints. Each of the wires of the netlist is initially assigned a unit weight. Thereupon, a rough placement process is performed consistent with physical constraints, whereby cells are assigned (x,y) locations according to the weights of each of the wires. Based on this rough placement process, wire lengths can be determined. The capacitance at each wire is then determined as a function of the wire length and the load capacitance(s) associated with that wire. Consequently, the performance of the design can be calculated based on the wire capacitances. The weights of the wires are then adjusted which causes the cells to be spaced apart according to the new weightings. A number of iterations are performed to adjust the weights and cell spacing in order to improve performance characteristics. In conjunction with adjusting the weight, the present invention also scales up/down the size of one or more of the gates. After a gate is scaled up/down, the wires are then iteratively examined; their weights are adjusted appropriately; and the cells are spaced apart according to the new weights. This entire process of wire weight examination/adjustment, cell separation, and gate sizing is repeated until no further improvements are forthcoming or until a pre-designated number of iterations have been completed.